Ò׽ؽØÍ¼Èí¼þ¡¢µ¥Îļþ¡¢Ãâ°²×°¡¢´¿ÂÌÉ«¡¢½ö160KB

»ù±¾ÔËËãµ¥ÔªµÄ¸ß²ã´Î×ۺϣºC/C++ to RTL

±¾ÎÄÒÔ¼Ó·¨ÎªÀý£º[code]
//----------------------------------------------------
//adder.c
//---------------------------------------------------
void adder(int a, int b, int *sum)
{
        *sum = a + b;
}
[/code][size=3]
[/size]
HLS¹¤¾ß£¨AutoPilot£©×ÛºÏÖ®ºóµÄ½á¹û£º[code]
//---------------------------------------------------
//adder.v
//--------------------------------------------------
`timescale 1 ns / 1 ps
module adder (
        a,
        b,
        sum
);
input  [31:0] a;
input  [31:0] b;
output  [31:0] sum;
assign sum = (b + a);
endmodule //adder
[/code][size=3]
[/size][code]
//---------------------------------------------------
//adder.vhd
//---------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.AESL_components.all;
entity adder is
port (
    a : IN STD_LOGIC_VECTOR (31 downto 0);
    b : IN STD_LOGIC_VECTOR (31 downto 0);
    sum : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of adder is
begin
    sum <= esl_add(b, a);
end behav;
[/code][size=3]
[/size]
±¸×¢£º¼Ó¼õ³Ë³ý¡¢Î»ÔËËã¡¢Âß¼­ÔËËãµÈµÈ»ù±¾µÄC/C++ÔËËã¶¼¿ÉÒԺܷ½±ãµÄÓÃAutoPilot×ۺϳɶÔÓ¦µÄRTL´úÂ루verilog/vhdl)[/size]


Ïà¹ØÎĵµ£º

W3C¶ÔÓÚCSS¼°ä¯ÀÀÆ÷Ö®¼äµÄ¼æÈÝÐÔÎÊÌâ½â¾ö·½°¸

ÎÄÕÂÀ´×Ô£ºhttp://mayer.vokaa.com/archives/16
¶ÔÓÚÒ»¸öǰ¶Ë¹¤×÷Õߣ¬¶¼ÖªµÀ·ûºÏW3C¹æ·¶¶ÔÓÚÍøÒ³µÄ¿çä¯ÀÀÆ÷¹¤×÷´øÀ´ºÃ´¦£¬²¢ÄÜÊ¹ÍøÒ³ÔÚ²»Í¬µÄä¯ÀÀÆ÷Ö®¼ä»¥Ïà¼æÈÝ¡£
ÔÚÕâÀïÎÒÃÇÒ»Ò»Áоٻ¥ÁªÍøÉÏËùÌṩµÄ½â¾ö°ì·¨¼°Ò»Ð©ÎÒ¸öÈ˵Ľ¨Ò鼰ʵ¼ù°¸Àý¡£
Æäʵ£¬ÏÖÔÚ¶àÊýÈ˶¼»áʹÓÃHackµÄ·½·¨½â¾ö£¬µ«Èç¹ûDIVºÍCSSµÄ½á¹¹ÇåÎú¡¢ºÏÀí£ ......

C+C C×C

1.CÓïÑÔÖУ¬long±»´æ´¢ÎªËĸö×ֽڵIJ¹Â롣дһ¸ö³ÌÐò£¬·Ö±ð½«ÕâËĸö×Ö½ÚµÄÄÚÈÝÈ¡³ö£¬ÒÔ16½øÖƵķ½Ê½ÏÔʾÔÚÆÁÄ»ÉÏ¡£³ÌÐòËùÐèµÄlongÓÉÓû§´Ó¼üÅÌÊäÈ룬0±íʾÊäÈë½áÊø¡£
³ÌÐòÔËÐÐЧ¹ûÈçÏ£º
input n: 12345678<»Ø³µ>
hex: 00 BC 61 4E
input
n: -12345678<»Ø³µ>
hex: FF 43 9E B2
input n: 0<»Ø³µ& ......

¡¾C/C++¡¿staticºÍconstµÄ±È½ÏºÍ½âÊÍ

ת
ÔØ×Ôhttp://www.builder.com.cn/
 
       static
ÊÇc++Öкܳ£ÓõÄÐÞÊηû£¬Ëü±»ÓÃÀ´¿ØÖƱäÁ¿µÄ´æ´¢·½Ê½ºÍ¿É¼ûÐÔ£¬ÏÂÃæÎÒ½«´Ó static ÐÞÊηûµÄ²úÉúÔ­Òò¡¢×÷ÓÃ̸Æð£¬È«Ãæ·ÖÎöstatic
ÐÞÊηûµÄʵÖÊ¡£
¡¡¡¡static µÄÁ½´ó×÷ÓÃ:
¡¡¡¡Ò»¡¢¿ØÖÆ´æ´¢·½Ê½£º
¡¡¡¡static±»ÒýÈëÒÔ¸æÖª±àÒëÆ÷£¬½«±ä ......

C ÔËËã·ûºÍ½áºÏÐÔ

CÓïÑÔÖеÄÔËËã·û¼°ÓÅÏȼ¶ÊǺÜÖØÒªµÄ£¬Ò»¶¨ÒªÀÃÊìÓÚÐÄ£¡
ÓÅÏȼ¶ ÔËËã·û º¬Òå ÒªÇóÔËËã¶ÔÏó¸öÊý ½áºÏ 1 ()
[]
->
. À¨ºÅÔËËã·û
ϱêÔËËã·û
½á¹¹Ìå³ÉÔ±ÔËËã·û ......

Can C beat RTL?


http://www.edn.com/article/457428-Can_C_beat_RTL_.php 
With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue but as a way to accelerate the inner loops of numerical algorithms, either in conjun ......
© 2009 ej38.com All Rights Reserved. ¹ØÓÚE½¡ÍøÁªÏµÎÒÃÇ | Õ¾µãµØÍ¼ | ¸ÓICP±¸09004571ºÅ