Can C beat RTL?

http://www.edn.com/article/457428-Can_C_beat_RTL_.php 
With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue but as a way to accelerate the inner loops of numerical algorithms, either in conjunction with or in place of the traditional DSP chip. There’s a problem, however. You code for a DSP chip in C, and you implement it using a conventional software tool chain with familiar software debugging tools. You configure an FPGA starting in Verilog or VHDL (very-high-speed-integrated-circuit-hardware-description language)—superficially similar to C but in practice profoundly different—and you implement it using a hardware design flow. The two approaches require different skills.
Enter ESL (electronic-system-level) tools. An ESL synthesis tool lets you write your code in C, automatically synthesize RTL (register-transfer-level) logic from the C, and then feed the RTL into your FPGA flow. In reality, such tools meet with skepticism because people suspect them of poor quality of results, unreliability, and other vices. Is that assessment fair, though? BDTI (Berkeley Design Technology Inc) wanted to find out.
The company last month released the first results of its certification program for high-level synthesis tools. The first evaluation covers AutoESL’s AutoPilot and Synfora’s Pico. The bottom line in BDTI’s findings was that both tools produced results in a reasonable amount of time and that both performed much better than software on a DSP chip. The tools were comparable in density and performance with hand-coded RTL. The fine print reveals a wealth of information below that level, however.
Unsurprisingly, both ESL vendors produced designs with about 40 times the throughput of the best BDTI engineers could do on a Texas Instruments DM6437 DSP chip. Surprisingly, in a separate test with a smaller design, results from the ESL flow